The present invention is generally directed to an integrated circuit packaging configuration exhibiting greatly increased packaging densities over that which is presently obtainable. More particularly, the present invention relates to a packaging method for electronic integrated circuit chips, particularly very large scale integrated circuit (VLSI) devices on a substrate also having a removable polymer film overlying the chips on the substrate and providing a means for supporting interchip and intrachip connection conductors. Even more particularly, the present invention relates to removable interchip and intrachip interconnection means which provide wafer scale integration packaging densities while at the same time, rendering it possible to reconfigure the system of chips by removing the polymer film and redepositing a second film layer with a different interconnection arrangement.
In the packaging of very large scale integrated circuit devices, a great deal of space is taken up by mechanisms for interconnecting one chip to an adjacent device. This makes the packaging of integrated circuit devices and electronic components based thereon larger than necessary. As a result of this, many individuals are involved in the development of so-called wafer scale integration processes. However, the efforts expended in these directions have generally tended to be limited by the problem of yield. Because a certain number of chips or dies on a wafer are often found to be defective, the number of wafers that are produced that are completely usable is generally lower than is desired. Furthermore, there still exists the problem of interconnecting the various chips on a wafer and the concomitant problem of testing a large system, such as results when a number of highly complicated individual integrated circuit components are interconnected. Accordingly, it is seen that it would be very desirable to construct wafer scale integrated circuit packages from individual, easily testable integrated circuit chips. It is to this end that the present invention is directed.
More particularly, the present invention is directed to a configuration and method employing a polymer film overlay. This film covers a plurality of integrated circuit chips adjacent to one another on an underlying substrate. Furthermore, the polymer film provides an insulative layer upon which is deposited a metallization pattern for interconnection of individual circuit chips. Furthermore, a significant advantage of the system of the present invention is the ability to remove one or more of these interconnection layers so as to provide a multitude of arrangement and testing capabilities.
One configuration of the present invention involves the disposition of a polymer film over a plurality of integrated circuit chips affixed to an underlying substrate. A method for carrying out such a process is described in application Ser. No. 912,458. An apparatus for carrying out a polymer overlay process, as preferred in the practice of the present invention, is also disclosed therein. In particular, the inventions disclosed therein solve significant problems with reseect to high temperature processing and the requirement for excellent compliance of a plastic material to an irregular surface. Accordingly, aforementioned application Ser. No. 912,458 is hereby incorporated herein by reference.
Likewise, in the practice of the present invention, it is desirable to provide via openings or apertures in the polymer dielectric layer so as to be able to provide electrical connection between various parts of a chip or between several chips. Accordingly, application Ser. No. 912,455 discloses therein a preferred embodiment for carrying out a process for providing such apertures. Likewise, application Ser. No. 912,455 is also hereby incorporated herein by reference. Both of these applications are assigned to the same assignee as the present invention.
In general, the problem solved by the present invention is that of interconnecting integrated circuit chips. In recent years, this problem has been compounded by the dramatic increase in the number of interconnects associated with VLSI circuitry. Since very large scale integrated circuits incorporate a large portion of the total system into one integrated circuit, more interconnects must be provided to the VLSI circuit.
At the same time, circuit complexity is increasing, reduced circuit dimensions are also desired and employed since they lead to higher speed devices. To promote speed, interconnection from one chip to another must be accomplished with a minimum of capacitive loading and a minimum of interconnect length. Capacitive loading tends to slow down signal transmission such that high speeds attained on the chip cannot be maintained in communicating from one chip to another. Interconnection length between chips also contributes to propagation delay due to greater capacitive loading effects in the dielectric medium due to circuit length and also due to a self inductance of the interconnection circuit.
Space, or "chip real estate", is another important consideration even in such devices as the personal computer. A simple calculation based on the amortized cost of each card slot in a regular personal computer indicates that the value of the card slot is approximately $400. Obviously, in portable equipment, size and weight are of primary importance. Even in large computer and super computer systems, size and signal speed are very significant.
In many applications, it is necessary to provide intimate contact between a semiconductor device and the substrate to which it is mounted. Intimate contact is highly desirable to assure the best electrical connection and also the best thermal conductivity for the purpose of heat removal. In those interconnection technologies, where chips are mounted upside down, elaborate structures must be provided for removal of heat or for making electrical connection to the substrate of the chip.
The reliability of an electronic system is only as great as the chain of reliabilities of each of the interconnects between the integrated circuit chip and the outside world. In a conventional system, an integrated circuit chip is placed in a package; then, wire bond or tape-automated bonding methods are used to make interconnections from the pads of the chip to the pins of the package. The pins of the package are then connected to the runs of a printed circuit board by soldering. To connect two integrated circuits together, the runs of the printed circuit board are subsequently soldered to the pins of a second package and the pins of the second package are bonded to the pads of the integrated circuit thereon. It can be seen that a multiplicity of interconnects have been required simply to connect one integrated circuit to another. For the reasons discussed above, this is not desirable.
Interconnection is often provided by several different methods. The first has already been mentioned above, where interconnection is provided by wire bonding from the pads of the chip to the pins of the package. Generally, this method is used to package only a single chip. Multiple chips have been interconnected in hybrid circuits in accordance with the following process. A substrate is processed either by thick or thin film methods to provide interconnect wiring on the substrate; chips are mounted on the substrate; and wire bonding is used to make connections from the pads of the integrated circuit chip to the wiring of the hybrid substrate. In this method, run-to-run spacing on the substrate is typically approximately 20 mils (10 mils for the conductor and 10 mils for the gap between the conductors). This leads to a pitch discrepancy between pads on the chip and the runs required to make interconnections between the chips. It is, therefore necessary that the chips be separated by relatively large distances to accommodate the intercomponent wiring. Ceramic multilayers with chips mounted by solder bump methods comprise another interconnection method. In this method, alternate layers of conductor and ceramic insulator are pressed together in the green state and fired to form a multilayer structure. Chips are provided with solder bumps on each pad and subsequently mounted upside down so that the solder bump positions on the chip correspond to interconnect areas on the ceramic multilayer. While this method has provided relatively high density interconnections, it has several limitations. Firstly, the chips must be specially processed in order to provide them with the solder bump. Secondly, the conductor areas are defined by screen printing methods, and the required vias are defined by mechanical punching methods. In general, these methods tend to suffer from reliability and repeatability problems. Thirdly, the green ceramic shrinks by approximately 20% during the firing process. All these factors contribute to a relatively low interconnect density on any given layer. In order to achieve high overall packing density, it is necessary to provide a large number of layers (10 to 20 such layers not being uncommon in a complex multilayer ceramic substrate). Heat removal is an additional problem since the solder bumps do not provide sufficient heat removal and some kind of elaborate mechanical connection usually must be made to the backs of the chip. Since a great deal of tooling is required, this method is not amenable to low-cost, low-volume production. Finally, an additional problem exists in that the size of the solder bump presently limits pad separation to approximately 10 mils.
In a process seeking to achieve some of the same objectives as the present invention, semiconductor chips are mounted on a substrate, and a layer of material such as polytetrafluoroethylene (PTFE) is pressed over the tops of the chips and around the chips so that the chips are completely encapsulated in this layer. Holes are etched in the encapsulating layer corresponding to pad positions on the chips. Metallization is applied and patterned to form interconnections. However, the present invention is significantly different from such processes for the following reasons. In this process, known as semiconductor thermodielectric processing, the chips are completely embedded in PTFE material so that no overlay layer as such exists. This makes it impossible to repair an assembly since the chips cannot be removed. Even if a chip could be removed, the remaining chips would still be encapsulated in the PTFE material and there would be no way to install a replacement chip and to interconnect that chip to the rest of the system. In addition, there is no provision in the semiconductor thermo-dielectric processing method for a removable metallization layer which is selectively etched, thus protecting the underlying circuit while assuring complete removal of the metallization layer. In addition, the semiconductor thermodielectric processing method faces two other problems. First, by encapsulating chips in a polymer, a high degree of stress is created by the difference in thermal expansion coefficients. Second, the thickness of the polymer over the top of the chips is governed solely by the thickness of the chip and the tooling which encapsulates the chips. Variations in chip thickness lead to variations in the thickness of the polymer over the chip.
An additional problem with ceramic multilayer configuration as well as with hybrid devices on ceramic substrate is the relative dielectric constant associated with ceramic materials which is approximately 6. This also leads to higher capacitive loading and increased propagation delay as compared with polymer dielectrics which possess a typical relative dielectric constant of between about 2 and about 4.